1. Field of the Invention
The present invention relates to a data processing apparatus.
Priority is claimed on Japanese Patent Application No. 2011-024819, filed Feb. 8, 2011, the content of which is incorporated herein by reference.
2. Description of the Related Art
All patents, patent applications, patent publications, scientific articles, and the like, which will hereinafter be cited or identified in the present application, will hereby be incorporated by reference in their entirety in order to describe more fully the state of the art to which the present invention pertains.
In an image processing apparatus included in an image pickup device such as a still-image camera, a moving-image camera, a medical endoscope camera, or an industrial endoscope camera, an image processing circuit, which performs a filtering operation and the like alternately using two line buffers, is disclosed, for example, in Japanese Unexamined Patent Application, First Publication No. H8-336114. In the above-described image processing circuit, a still image of one frame is divided into a plurality of blocks, and image processing is performed to each divided block. FIGS. 10A and 10B are diagrams illustrating a block division method in a pipeline process in accordance with the related art. When a still image of one frame is divided into a plurality of blocks as shown in FIG. 10A, a flow of image data to be processed within each divided block is continuous, but a flow of data between different blocks is not continuous as shown in FIG. 10B.
FIGS. 11A and 11B are diagrams illustrating an example of processing timings of a pipeline process in accordance with the related art. As shown in FIGS. 11A and 11B, there is a need for a procedure for resetting an image processing circuit and resetting a range of image data corresponding to the next block to be processed, or the like every time processing of one block is completed. When an operation of the image processing circuit is controlled for each block processing, a period of time loss in which the image processing circuit does not operate occurs during each block processing as described above. A loss time in which the image processing circuit does not operate affects a total processing time of a pipeline process of processing a still image of one frame.
Technology for reducing time loss in processing between blocks in a pipeline process is disclosed in Japanese Unexamined Patent Application, First Publication No. 2010-176606. FIGS. 12A and 12B are diagrams illustrating an example of processing timings of the pipeline process. In this technology, as shown in FIG. 12A, an interrupt signal (a process completion interrupt signal) indicating that a process by a processing circuit is completed for each processing circuit constituting a pipeline is output to a sequencer, which controls the entire pipeline process. As in FIG. 12B, every time the process completion interrupt signal is input from the processing circuit, the sequencer individually changes settings of the processing circuit. Thereby, the sequencer changes the settings of the processing circuit every time a process of each processing circuit for each block is completed, not every time processing of a divided block is started. In the technology of Japanese Unexamined Patent Application, First Publication No. 2010-176606, the sequencer changes the settings of each processing circuit for every processing circuit as described above, thereby reducing the time loss in processing between blocks and increasing the speed of the pipeline process for a still image of one frame.
Even when settings change after processing of one block is completed and then processing of the next block is started in a state in which the technology disclosed in Japanese Unexamined Patent Application, First Publication No. 2010-176606 is adopted in processing circuits constituting the pipeline, there is still a processing circuit in which time loss occurs among the processing circuits constituting the pipeline. For example, in a data processing apparatus having access to data stored in an external memory such as a dynamic random access memory (DRAM) connected to a common data bus by a burst transfer of direct memory access (DMA), a loss time is caused by a combination of a size (capacity) or configuration of a buffer for temporarily storing data included in the data processing apparatus and an amount of data to be transferred by a DMA transfer (a burst transfer). This is caused by the presence of a break (a burst boundary) in data on an external memory because the burst transfer is performed in units of predetermined burst widths.
Hereinafter, an example of the data processing apparatus in which a loss time occurs will be described. FIG. 13 is a block diagram illustrating an example of a schematic configuration of a data processing apparatus in which the loss time occurs in accordance with the related art. The data processing apparatus of the related art shown in FIG. 13 includes two buffers (buffers A and B), a DMA interface (I/F) for acquiring image data (data for block processing) necessary for block processing (image processing) stored in an external memory via a common data bus and writing (storing) the image data to one buffer, and a buffer read circuit for reading and block processing (image processing) of data for block processing stored in the other buffer, for example, to output the block-processed (image-processed) data to the next image processing unit of the pipeline.
In the data processing apparatus of the related art having the configuration as shown in FIG. 13, buffer operations (writing of data to one buffer and reading of data from the other buffer) are alternately switched using two buffers, so that data input/output are performed at the same time. A size of the buffer storing the data for block processing is the same buffer size (storage capacity) as the amount of data for block processing acquired by the DMA I/F from an external memory in a DMA transfer (a burst transfer). That is, the data processing apparatus of the related art shown in FIG. 13 is managed in units of burst boundaries of data for block processing capable of being stored in one buffer by one DMA transfer (one burst transfer).
FIG. 14A is a diagram illustrating an example when data is stored in the buffer included in the data processing apparatus in accordance with the related art. FIG. 14B is a diagram illustrating an example of processing timings for each block. In the data processing apparatus of the related art shown in FIG. 13, for example, data for block processing necessary to process a first block is stored in the two buffers by the DMA I/F in the order of Buffer A→Buffer B→Buffer A→Buffer B as shown in FIG. 14A. However, data for block processing to be burst-transferred from the external memory is not necessarily consistent with a burst boundary. As shown in FIG. 14A, the data for block processing is stored in the buffer across a burst boundary of data when the DMA I/F performs the burst transfer. Thus, the amount of data for block processing to be used in block processing of blocks may be small, for example, as in data for block processing stored in the buffer B by a fourth DMA transfer (a burst transfer) of processing of a first block or data for block processing stored in the buffer A by first and fifth DMA transfers (burst transfers) of processing of a second block. Data for block processing to be unused in block processing is also DMA-transferred by a burst transfer of the DMA I/F.
In the data processing apparatus of the related art, the buffer read circuit performs block processing by alternately reading data for block processing stored in the two buffers. Here, processing timings of the data processing apparatus of the related art when the data for block processing is stored in each buffer as shown in FIG. 14A will be described using FIG. 14B.
First, the DMA I/F stores data for block processing DMA-transferred (burst-transferred) from the external memory in the buffer A. If storing of the data for block processing to the buffer A is completed, the DMA I/F continuously stores the data for block processing transferred by the DMA transfer from the external memory in the buffer B.
In addition, if the data for block processing is stored in the buffer A by the DMA transfer, the buffer read circuit starts block processing of the first block by reading the data for block processing stored in the buffer A. If data for block processing is stored in the buffer B after the block processing of the first block using the data for block processing stored in the buffer A has ended, the buffer read circuit continues the block processing of the first block by continuously reading the data for block processing stored in the buffer B.
Thereafter, if the block processing of the first block using the data for block processing stored in the buffer A has ended, the DMA I/F continuously DMA-transfers data necessary for the block processing of the first block from the external memory and stores the data for block processing in the buffer A. Thereafter, the DMA I/F sequentially performs a DMA transfer of the data necessary for the block processing of the first block from the external memory and storing of the data in one buffer.
In addition, if the data for block processing is stored in the buffer A after the block processing of the first block using the data for block processing stored in the buffer B has ended, the buffer read circuit continues the block processing of the first block by continuously reading the data for block processing stored in the buffer A. Thereafter, the buffer read circuit sequentially performs the block processing of the first block using the data for block processing stored in the buffer B and the buffer A.
If storing of last data for block processing to be used in block processing of the first block (data for block processing stored in the buffer B by a fourth DMA transfer in FIG. 14A) to one buffer is completed, the DMA I/F can start a DMA transfer of data for block processing to be used in block processing of the second block to be continuously processed next and storing of the data in the other buffer by making settings necessary to process the second block. Because the last data for block processing to be used in the block processing of the first block is stored in the buffer B, data for block processing to be used in the block processing of the second block is sequentially stored from the buffer A. More specifically, as shown in FIG. 14A, data is stored in the two buffers in the order of Buffer A→Buffer B→Buffer A→Buffer B→Buffer A.
In addition, after the block processing of the first block using the data for block processing stored in the buffer A has ended, the buffer read circuit continuously performs the block processing of the first block by reading the last data for block processing stored in the buffer B. The last data for block processing for performing the block processing of the first block is some (a fraction of) data for block processing within the data for block processing stored in the buffer B. Thus, the block processing of the first block using the last data for block processing stored in the buffer B ends at a comparatively early time. Then, the buffer read circuit is in a state in which the block processing of the second block to be processed next can be started.
However, when the state in which the block processing of the second block can be started has been reached, a DMA transfer of initial data necessary for the block processing of the second block from the external memory by the DMA I/F and storing in the buffer A are not completed. This occurs, for example, when a processing time of the last data for block processing of the first block stored in the buffer B is shorter than a DMA transfer time of the initial data for block processing of the second block to the buffer A as shown in FIG. 14B.
Thus, the buffer read circuit waits until the initial data necessary for the block processing of the second block is stored in the buffer A for the block processing of the second block. There is a problem in that a time for which the buffer read circuit waits to start the block processing (or a delay time of a block processing start) until the data necessary for the block processing is stored in the buffer, that is, until the DMA transfer (the burst transfer) is completed, becomes a loss time in the data processing apparatus.
In addition, if the initial data for block processing of the second block is stored in the buffer A, the buffer read circuit starts the block processing of the second block by reading the data for block processing stored in the buffer A. The buffer read circuit is in a state in which the block processing of the second block is continued by continuously reading the data for block processing stored in the buffer B after initial block processing of the second block using the data for block processing stored in the buffer A has ended.
However, when the initial data for block processing of the second block is (a fraction of) data within the data of block processing stored in the buffer A as shown in FIG. 14A, the block processing of the second block using the initial data for block processing stored in the buffer A ends comparatively early. Because a block processing time of the buffer A of the second block is shorter than a DMA transfer time of the buffer B of the second block when a state in which the block processing of the second block is continued by reading the data for block processing stored in the buffer B is reached, a DMA transfer from an external memory of data for block processing necessary for block processing of the second block by the DMA I/F and a storing in the buffer B are not completed.
Thus, the buffer read circuit waits until the data necessary for the block processing of the second block is stored in the buffer B for the block processing of the second block. There is a problem in that a time, for which the buffer read circuit waits to start the block processing until the data necessary for the block processing is stored in the buffer, becomes a waste of time (time loss) in the data processing apparatus. This loss time affects the entire processing time of the pipeline process.
FIG. 15 is a block diagram illustrating another example of a schematic configuration of the data processing apparatus in accordance with the related art. To increase the possibility of reducing the loss time, the number of buffers to be mounted in the data processing apparatus may be increased from 2 to 4 (buffers A, B, C, and D) as shown in FIG. 15. However, a circuit scale of the data processing apparatus is increased if the number of buffers mounted in the data processing apparatus is increased.